一种用于亚微米多晶栅TiSi电阻优化的方法

A Method to Reduce TiSi Resistance on Polysilicon-gate in Submicrometer CMOS IC

在亚微米工艺中,多晶栅TiSi工艺是降低接触电阻的常用方法。但是TiSi的生长与衬底的掺杂浓度相关,对多晶栅的掺杂剂量有很高的要求。由于光刻工艺中存在的套刻偏差,使得后续源漏注入剂量会在多晶栅上有所偏差,影响了后续TiSi在多晶栅上的生长。文章采用多晶栅上生长一层LPCVD SiN作为掩蔽层的方法,避免了由于光刻套刻偏差引入的注入剂量偏差,改善了后续多晶栅上TiSi的生长。通过对As注入和P注入在不同SiN厚度掩蔽层下穿透率的研究发现40 nm左右基本可以阻挡95%的N+S/D As注入剂量而保留80%的多晶栅P注入剂量。该种掩蔽层方法有很多优点:源漏注入的条件不用更改;多晶栅注入的可调节剂量范围大大增加,可以更好地保持重掺杂多晶栅特性。

The polysilicongate titanium silicide process has been used more and more universally in submicron manufacturing process. But TiSi growth has correlation with doping of substrate. Poor overlay precision caused the polysilicongate implant dose out of control during source/drain implant process. The abnormal of implant dose of polysilicongate will affect the growth of TiSi on polysilicon gate, and cause the resistance of TiSi increases. This paper proposed a method to improve the TiSi resistance on submicron polysilicongate. Though growing a SiN barrier layer on polysilieongate, effectively reduce the abnormal of implant dose, and then guarantee the stability of TiSi growth on polysilicongate and resistance. Using this SiN barrier layer can hold up 95% as dose and hold 80% P dose. This SiN barrier layer has a lot of advantages： such as keep source/drain implant condition stability; increase the adjustment region of polysilicongate implant dose and keep the characteristic of the doped polysilicongate.