MIPS_RAC终端测试于0.13μm逻辑平台的工艺优化

MIPS_RAC Performance Optimization on a 0.13 μm Logic Process Platform

高清数字电视的HD-DVR机顶盒已经成为了全球发展的趋势,MIPS_RAC终端测试作为其中缓存的反应速度的主要芯片参数,其工艺窗口直接关系到机顶盒成品率的高低和稳定。文章研究了MIPS_RAC终端测试与器件速度之间的关系,并定义了MIPS_RAC在0.13μm的通用逻辑工艺平台上的工艺安全范围。

The high resolution digital TV set-top box has become the trend of the set-top in the world. As the speed performance of the cache in the set-top box the yield of MIPS RAC bin directly affects the performance and the production yield of the set-top box. This paper presents the experimental study on the correlation between MIPS RAC and device speed, and figure out the safe device window on the 0.13 μm logic platform.