基于AMBA总线的高性能QDRⅡ SRAM控制器设计

Design of High Performance QDRⅡ SRAM Controller Based on AMBA Bus

针对高速网络的需求,介绍了一种高速静态存储器QDRⅡSRAM,设计了一种基于AMBA总线的高性能QDRⅡSRAM控制器IP,具有良好的接口兼容性和可移植性。使用了深度为8×72位的写出FIFO与8×72位读入缓冲,增加了系统存取的效率,设计通过仿真及实际验证,能够良好应用于系统时钟为800 MHz的SOC环境中,满足功能和时序要求。

In the paper, QDR Ⅱ SRAM as a kind of high speed static radom access memory is introduced for the request of high speed internet, the paper designs a high performance IP of QDR Ⅱ SRAM controller based on AMBA bus which has good performance on interface compatibility and transplanting. Using 8 - 72 bit write out FIFO and 8 - 72 bit read in buffer to increase the access efficiency of system. It has been verified successfully in the simulation and fact, using in the SOC system of 800 MHz system clock well, meeting the requirements of function and timing.