基于VHDL的数字秒表设计

VHDL-based Design of Digital Stopwatch

当今社会正朝着电子市场发展,越来越多的电子产品应用于各个领域。而VHDL的发展也是飞速的,且越来越成熟。与传统的设计相比,VHDL采用自顶向下的设计方法,打破了软硬件的屏障,节约了大量的空间,降低了功耗,易于随时修改程序,拥有很好的可修改性和移植共享性,克服了传统设计的缺点。

Today’s society is moving in the electronics market, more and more electronic products used in various fields. But also the rapid development of VHDL, and more mature. Compared with the traditional design, VHDL using top-down design approach, breaking the barrier of hardware and software, saving a lot of space, reduced power consumption, easy to modify the program at any time, have a good transplant can be modified and shared resistance, to overcome the shortcomings of traditional design.