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An accurate RLGC circuit model for dual tapered TSV structure

An accurate RLGC circuit model for dual tapered TSV structure
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摘要 A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via （TSV） structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient. A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via （TSV） structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.
作者 魏祯 李晓春 毛军发
机构地区 Key Laboratory of Ministry of Education of Design and Electromagnetic Compatibility of High-Speed Electronic Systems
出处 《Journal of Semiconductors》 EI CAS CSCD 2014年第9期136-142,共7页 半导体学报（英文版）
基金 Project supported by the National Natural Science Foundation of China(No.61234001) the Shanghai Science and Technology Committee(No.13511500900) the Specialized Research Fund for the Doctoral Program of Higher Education(No.20120073130003)
关键词 tapered TSV RLGC circuit model numerical integration method current continuity eddy effect tapered TSV RLGC circuit model numerical integration method current continuity eddy effect
分类号 TN402 [电子电信—微电子学与固体电子学]
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参考文献17

  • 1Banerjee K, Souri S J, Kapur P, et al. 3-D ICs: a novel chip design for improving deep-submicrometer interconnect perfor- mance and systems-on-chip integration. Proc IEEE, 2001, 89: 602.
  • 2Davis W R, Wilson J, Mick S, et al. Demystifying 3D ICs: the pros and cons of going vertical. Design and Test of Computers IEEE, 2005, 22:498.
  • 3Beica R, Siblerud P, Sharbono C, et al. Advanced metallization for 3D integration. Electronics Packaging Technology Confer- ence, 2008, (10): 212.
  • 4Yu G. Study of DRIE's application in through silicon via (TSV) technology. Su Zhou University, 2009.
  • 5Leung L L W, Chen K J. Microwave characterization and model- ing of high aspect ratio through-wafer interconnect vias in silicon substrates. IEEE Trans Microw Theory Tech, 2005, 53:2472.
  • 6Savidis I, Friedman E G. Electrical modeling and characteriza- tion of 3-D vias. IEEE International Symposium on Circuits and Systems, 2008:784.
  • 7Savidis I, Friedman E G. Closed-form expressions of 3-D via re- sistance, inductance, and capacitance. IEEE Trans Electron De- vices, 2009, 56:1873.
  • 8Katti G, Stucchi M, De Meyer K, et al. Electrical modeling and characterization of through silicon via for three-dimensional ICs. IEEE Trans Electron Devices, 2010, 57:256.
  • 9Savidis I, Alam S M, Jain A, et al. Electrical modeling and char- acterization of through-silicon vias (TSVs) for 3-D integrated cir- cuits. Microelectron J, 2010, 41:9.
  • 10Xu C, Li H, Suaya R, et al. Compact AC modeling and perfor- mance analysis of through-silicon vias in 3-D ICs. IEEE Trans Electron Devices, 2010, 57:3405.
Journal of Semiconductors
2014年 第9期

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