摘要
介绍了在第二代同轴电缆宽带接入技术HINOC2.0中信道编码LDPC码译码器的设计难点,针对方案中高吞吐量的难点,提出了几种译码器的硬件结构,并且给出每一种结构在满足吞吐量要求时的资源消耗。为译码器的硬件实现提供参考,并给出了硬件资源分析和仿真结果作为理论依据。
The difficulties in the design of LDPC decoder which is adopted in HINOC2.0 system is introduced. According to its high-throughput requirement, several hardware structures are proposed with the resource consumption analysis of each structure. As a reference for the deeoder hardware implementation,the hardware resource analysis and simulation results are given.
出处
《电视技术》
北大核心
2014年第17期22-24,42,共4页
Video Engineering
