摘要
给出一种基于ASIC的长期演进(LTE)速率匹配并行设计方案。速率匹配是LTE物理层比特级处理流程中重要的一步,LTE的高峰值速率要求其并行处理。已有的并行设计方案需要用到大量的小容量RAM,用于ASIC时会增加片上存储的面积。深入分析速率匹配算法的特性,通过数据分组和添加少量哑元,只用了少量的RAM实现了8 bit并行处理。在Synopsys VCS平台仿真并用Synopsys DC工具综合,结果表明本方案性能满足LTE宏站(三个20 MHz扇区)的需求,而存储面积相比于现有的使用大量小RAM的方案显著减小。
A parallel implementation scheme of LTE rate matching prosented based on ASIC.Rate matching is a vital step in the bit-level processing of LTE physical layer,which requires parallel processing due to the high peak rate of LTE.The existing parallel design applies a large number of small-capacity RAMs,which significantly increase storage area.The characteristics of the rate matching algorithm were deeply analyzed.By data grouping and adding dummy bits,only a small amount of RAMs were used to achieve a 8 bit parallel processing.The simulation and synthesis result by Synopsys VCS platform combined with Synopsys DC tools shows that its performance meets the requirement of macro cell enabling three 20 MHz LTE sector,while the storage surface is significantly reduced compared to the existing solutions using many small-capacity RAMs.
出处
《科学技术与工程》
北大核心
2014年第22期56-61,共6页
Science Technology and Engineering
基金
国家自然科学基金(61373026)
国家重大科技专项(2013ZX03003013-003)资助
