IEEE 802.16e标准中LDPC编码的实现与仿真

The implementation and simulation of IEEE 802.16e LDPC coding

根据IEEE802.16e标准中LDPC编码的定义,提出了一种利用高速状态机来实现编码的快速算法。在Quartus II下使用Verilog HDL实现了该算法并进行了时序仿真。仿真结果表明,设计具有良好的实时性,克服了以往设计中预处理复杂、消耗逻辑资源多的缺点。最后利用MATLAB对该设计与DVB-S2缩短码的BER性能进行了比较,分析了制约DVB-S2缩短码性能的因素。

According to the definition of IEEES02.16e LDPC coding, this paper proposes a high-speed state machine to achieve fast coding algorithm. This algorithm is realized under the Quartus II environment by using Verilog HDL and timing simula- tion is also made. The results show that the design has a good real-time performance. It overcomes the shortcomings of complex pre-processing and consumption of logic resources. Finally, the BER performances between this design and shortened DVB-S2 codes are compared under MATLAB. The facts which can restrict shortened DVB-S2 code performance are also analyzed.