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浮结位置对4H-SiC浮结结势垒肖特基二极管特性的影响(英文)

Effects of Floating Junction Position on the Performances of 4H-SiC Floating Junction Schottky Barrier Diodes
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摘要 同质外延层厚度、铝离子注入深度及光刻偏差会导致4H-SiC浮结结势垒肖特基二极管中浮结位置偏离最优值,器件特性变差。通过数值模拟的方法对浮结横向及纵向位置偏差对其电学特性的影响进行了研究。纵向方向,两个梯形电流分布使得通态比电阻随着浮结由主结向下移动而缓慢增加。击穿电压由距离主结3.5μm处的607V增加到5.6μm处的1 030V。随着浮结进一步向下移动,击穿电压急剧下降,最终保持在550V。这个变化趋势可以通过浮结在漂移区中不同纵向位置的电场分布进行解释。横向方向,浮结与主结对准及交叉放置时电场呈周期性分布且非常均匀,浮结均匀的承担了电压,击穿电压较高。浮结横向偏差时,电流导通路径变长,通态比电阻增加。计算结果表明,浮结与主结对准与交叉放置时Baliga品质因子达到了9.8×109 W/cm2,16%高于1.3μm横向偏差时的8.2×109 W/cm2。因此,4H-SiC浮结结势垒肖特基二极管设计时必须考虑工艺偏差对其特性的影响。 The homoepitaxy layer thickness, aluminum ion implantation depth and alignment deviation of lithography can cause floating junction departure from their optimal position in 4H-SiC floating junction Schottky barrier diodes. The effect of floating junction longitudinal and horizontal deviation on its electrical characteristic is discussed by numerical simulation. In longitudinal direction, two trapezoidal current profiles enable specific on-resistance to slowly increase when floating junction moves downward from the main junction. Breakdown voltage increases from 607 V to 1 030 V at 3.5 μm and 5.6 μm of the distance from the main junction, respectively, and then sharply drops to a stable voltage of 550 V. The reasons can be explained by electric field distribution at different floating junction longitudinal positions. In horizontal direction, the electric field is uniform and periodically distributed when the floating junction and main junc- tion are aligned and staggeringly placed, and the floating junction evenly shares the voltage drop, so break- down voltage is higher than that in longitudinal position. Current conduction length in the drift region becomes longer for horizontal deviation, resulting in specific on-resistance to be increased. The calculations show that in case of alignment and staggered place, the highest Baliga's figure of merit 9.8 × 10^9 W/cma is obtained, which is 16% higher than the lowest 8.2 × 10^9 W/cm2 at 1.3 μm horizontal deviation. Therefore, floating junction deviation during fabrication process needs to be fully controlled for 4H-SiC FJ-JBS design.
出处 《固体电子学研究与进展》 CAS CSCD 北大核心 2014年第4期315-320,共6页 Research & Progress of SSE
基金 国家自然科学基金资助项目(60876050)
关键词 碳化硅 浮结 位置偏差 数值模拟 silicon carbide(SiC) floating junction position deviation numerical simulation
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