基于改进型Montgomery模块的RSA算法及其Verilog模型的实现

Realization of RSA algorithm and its Verilog model based on modified Montgomery module

详细分析了RSA加密算法的原理及优化方法,提出一种高效可行改进型硬件模块的实现方案,并给出了效率分析以及在硬件平台上的仿真结果分析;通过仿真分析发现,相比以往的算法模型,该方案在时序以及面积上均做到了相当程度的优化,硬件的占用面积大幅度减少,具体的性能及功耗、稳定性有较大提高,为工程应用提供了良好的借鉴。

The principles and optimization method of RSA encryption algorithm are analyzed in detail in this paper. A feasi-ble and efficient implementation scheme of modified hardware modules is proposed. The analyses of efficiency and simulation re-sults on the hardware platform are conducted. The simulation results show that,compared with the previous algorithm models, the scheme has already been optimized to a certain extent in both the time sequence and the volume,reduced the area that the hardwares used to occupy significantly,improved performance,power consumption,stability greatly and provided a good reference for engineering applications.