面向硬件实现的一种视频实时缩放算法

A Hardware Implementation Oriented Algorithm for Real-Time Video Scaling

为了满足对高分辨率图像缩放处理速率和功能的要求,依据复杂度高、效果好的双立方内插值(BI-CUBIC)提出了一种面向硬件实现的插值算法,在该算法原理基础上结合高度流水线结构搭建系统架构,用XILINX软件设计验证各功能模块后将系统实现在该公司的Virtex5-110T芯片上。测试证明该FPGA芯片能够实现对任意比例尺寸图像的任意比例缩放功能,占用较少芯片资源同时处理能力达到1 080 pixel每秒48帧。

To meet the requirements of high-resolution image scaling rate and function, a hardware architecture for the interpolation algorithm based on Bicubic Interpolation （BI-CUBIC）was proposed for its high complexity and good quality. The system was built based on the principle of the algorithm with highly pipelined architecture, and finally im- plemented in the XILINX VirtexS-110T chip after each module had been designed and verified on XILINX software. The tests show that the FPGA chip can achieve any arbitrary proportion scaling function with any size pictures, and occupy less chip resources while the processing capacity is able to reach 1 080 pixel 48 frames per second.