基于可逆触发器的可逆移位寄存器设计方法

Design Method for Reversible Shift Register Based on Reversible Flip Flop

为了进一步提高可逆时序逻辑电路设计方法的通用性和改善可逆电路性能指标,以可逆主从D触发器为基本单元,通过将时钟信号及垃圾位信号级联再利用,提出了一种可逆串行移位寄存器优化设计方案。在此基础上,通过目标函数构造及变换构建带有移位控制的单元模块,设计了满足串行输入串/并行输出功能的n位可逆双向移位寄存器。设计结果表明,采用方法所设计的可逆移位寄存器具有较优的性能指标,且对于双向移位寄存器综合具有较好的通用性。

To improve the generality of synthesis methods of reversible sequential logic circuits and circuit performance indicators,an optimized design of reversible serial shift register is presented based on master-slave D flip-flop,which constructs serial shift registers by cascading and reusing the clock signal and garbage bits.And on this basis,the objective function is constructed and transformed to build modules with shift control and design the n-bit reversible register realizing the function of bidirectional serial-in parallel-out and serial-out parallel-out.The results show that the proposed reversible serial shift register has better performances and the method has preferable generality in synthesizing bidirectional registers.