基于SDRAM的大容量FIFO的方案设计

Design of High-Capacity FIFO Based On SDRAM

在数据高速采集系统中缓存是一个关键的部分,随着数据量的增加和速度的提高,对缓存的容量和速度提出更高的要求。采用Altera公司的Cyclone系列的FPGA设计了大容量高速率的可随时读写的FIFO,并将设计嵌入到数据采集系统中,完成了数据的存储功能。最后以QuartusII为平台进行设计,用Modelsim软件进行仿真,并已经应用到某型号设计中,达到了预期的目标。

Cache is an important component in high-speed data acquisition systems. The capacity and speed requirement of cache increase with the increasing of data capacity and rate nowadays. A high-capacity and high-speed FIFO is designed based on Altera＇s FPGA of Cyclone series. The design is embedded into the data acquisition system to accomplish the function of data storage. The design is completed with Quartus II platform and is simulated with Modelsim, and works well as expected in a certain project.