摘要
The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system performance,a modified scheme is presented to decline the resource consumption without too much degradation on the signal to noise ratio（SNR）.Theoretical analysis and numerical results demonstrate that compared to the traditional design,the proposed scheme could save dozens of memory resources.The scheme also includes some selectable parameters to achieve desired performance in various circumstances.Different from previous work in DDCs that concentrates mostly on the structure design,this paper considers special applications such as ultra-low symbol rate receivers.
The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system performance,a modified scheme is presented to decline the resource consumption without too much degradation on the signal to noise ratio（SNR）.Theoretical analysis and numerical results demonstrate that compared to the traditional design,the proposed scheme could save dozens of memory resources.The scheme also includes some selectable parameters to achieve desired performance in various circumstances.Different from previous work in DDCs that concentrates mostly on the structure design,this paper considers special applications such as ultra-low symbol rate receivers.
基金
Supported by the National Natural Science Foundation of China(60972018)
