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一种ADC积分非线性参数内建自测试方案 被引量:1

A BIST Scheme for INL Parameter Testing of ADC
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摘要 针对ADC(模数转换器)静态参数中积分非线性参数测试的问题,提出了一种快速测试的内建自测试方案。该方案利用数字谐振器和Σ-Δ调制器生成正弦测试源信号,依据FFT算法建立ADC的切比雪夫函数逼近模型,进而根据数学模型快速计算积分非线性参数。与传统的码密度直方图测试方案相比,所提出内建自测试方案硬件开销小,测试速度快,易于片上集成。实验结果验证了该方案的有效性。 Aiming at the static integral nonlinearity (INL) parameter testing of analog to digital converter (ADC), a novel fast built-in self test (BIST) scheme is presented. The scheme uses the digital oscillator and Sigma-Delta modulator to generate the testing source signal on chip and builds the Chebyshev polynomials model for ADC according to the fast Fourier transform(FFT), and then computes the INL parameter by using the ADC model. Comparing with the traditional histogram of ADC's out codes, the proposed BIST scheme has the advantages of high testing speed, low area overhead and easy integrating on chip. The results of simulation have proved the effectiveness of this scheme.
作者 谭子尤
出处 《微电子学》 CAS CSCD 北大核心 2014年第4期550-554,共5页 Microelectronics
基金 国家自然科学基金资助项目(61102089) 湖南省教育厅科学研究项目(10C1088)
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参考文献11

  • 1VORA S C, SATISH L. ADC static characterization using nonlinear ramp signal [J]. IEEE Trans Instru Measur, 2010, 59(8): 2115-2122.
  • 2ONG M S, KUANG Y C, LIAM P S, et al. Multisine with optimal phase-plane uniformity for ADC testing [J]. IEEE Trans Instru Measur, 2012, 61(3): 566-578.
  • 3HONG H C, SU F Y, HUNG S F. A fully integrated built-in self-test ∑-△ ADC based on the modified controlled sine-wave fitting procedure [J]. IEEE Trans Instru Measur, 2010, 59(9): 2334-2344.
  • 4袁超,赵元富,杜俊,鲍芳.一种混合信号SoC中模数转换器的内建自测试方案[J].微电子学与计算机,2010,27(1):123-126. 被引量:1
  • 5朱彦卿,何怡刚,阳辉,刘美容.一种高速ADC静态参数的内建自测试结构[J].湖南大学学报(自然科学版),2007,34(10):62-65. 被引量:6
  • 6PALFI V, KOLLAR I. Acceleration of the ADC test with sine-wave fit [J]. IEEE Trans Instru Measur, 2013, 62(5): 1256-1260.
  • 7EMMERT J M, CHEATHAM J A, JAGANNATHAN B, et al. An FFT approximation technique suitable for on-chip generation and analysis of sinusoidal signals [C]// 18th IEEE Int Syrup Defect Fault Tolerance VLSI Syst. Boston, MA, USA. 2003: 361-367.
  • 8ATTIVISSIMO F, GIAQUINTO N, KALE I. INL reconstruction of A/D converters via parametric spectral estimation [J]. IEEE Trans Instru Measur, 2004, 53(4): 940-946.
  • 9JIANG M, YANG B, HUANG R, et al. Multiplierless fast Fourier transform architecture [J]. Elec Lett, 2007, 43(3): 191-192.
  • 10李杰,杨军,李锐,吴光林.一种实现数模混合电路中ADC测试的BIST结构[J].微电子学,2004,34(4):466-468. 被引量:6

二级参考文献24

  • 1李杰,杨军,李锐,吴光林.一种实现数模混合电路中ADC测试的BIST结构[J].微电子学,2004,34(4):466-468. 被引量:6
  • 2杜俊,赵元富.VLSI可测性设计研究[J].微电子学与计算机,2004,21(10):189-192. 被引量:7
  • 3Le Jin, Chengming He. Fast implementation of a linearity test approach for high resolution ADCs using non- linear ramp signals[C]//IEEE 2004 International Symposium on Circuits and Systems. USA: State University, 2004.
  • 4Dominique Dallet, Jose Machado da Silva. Dynamic characterization of analog to digital converters [ M]. Berlin: Springer- Verlag Press, 2005.
  • 5Michael F, Toner, Gordon W Roberts. On the practical implementation of mixed analog- digital BIST[C]//IEEE 1995 Custom Integrated Circuits Conference. USA, Santa Clare, 1995 : 525 - 528.
  • 6Michael F Toner, Gordon W Roberts. A BIST schenae for a SN-R, gain tracking, and frequency response test of a sigma- delta ADC[J]. IEEE Transactions on circuit and systems II: Analog and digital signal processing, 1995, 42 (1):1-15.
  • 7Arabi K, Kaminska B. Oscillation built - In self- test(O- BIST) scheme for functional and structural testing of analog and mixed- signal integrated circuits[ C]// International Test Conference. USA, Washington, 1997:786 - 795.
  • 8Evan M Hawrysh, Gordon W Roberts. An integration of memory- based analog signal generation into current DFT architectures [ J ]. IEEE Transactions on Instrumentation and Measurement, 1998,47(3) :748 - 759.
  • 9Toner M F, Roberts G W. A BIST scheme for a SNR, gain tracking, and frequency response test of a sigma-delta ADC[J]. IEEE Trans Circ and Syst II:Analog and Digital Signal Processing, 1995 ; 42(1):
  • 10Renovell M, Azais F, Bernard S, et al. Hardware resource minimization for histogram-based ADC BIST[A]. 18thIEEE Proc VLSI Test Symp[C]. 2000. 247-252.

共引文献10

同被引文献14

  • 1Std I. IEEE standard for terminology and test methods foranalog-to-digital converters[S]. USA;IEEE Standard,2011.
  • 2Medawar S,H Ndel P,Bj Rsell N,et al. Input dependent in-tegral nonlinearity modeling for pipelined analog-digital con-verters [J]. IEEE Transactions on Instrumlentation & Meas-urement,2010,59( 10) :2609 -2620.
  • 3Medawar S, Handel P, Murmann B, et al. Dynamic calibra-tion of undersampled pipelined ADCs by frequency domainfiltering[J]. IEEE Transactions on Instrumentation & Meas-urement,2013, 62(62):1882-1891.
  • 4Rapuno S,Daponte P,Balestrieri E, et al. ADC parametersand characteristics-Part 6 in a seriesof tutorials in instrumen-tation and measurement [ J] . IEEE Transactions on Instru-mentation Measurement, 2005,8(5) : 44 -54.
  • 5Linnenbrink T E,Blair J,Rapuno S,et al. ADC testing-Part7 in a seriesof tutorials in instrumentation and measurement[J ]. IEEE Transactions on Instrumentation & Measure-ment,2006,9(2) ;39-49.
  • 6Kerz^rho V, Bernard S, Azas F, et al. A novel implementa-tion of the histogram - based technique for measurement ofINL of LUT-based correction of ADC [ J]. MicroelectronicsJournal,2013,44(9) :840 -843.
  • 7Analog Devices. AD6645/14 位/80 - 105 MSPS 模数转换器[M]. TX,USA:Analog Devices,2010.
  • 8Michaeli L, Michalko P, Saliga J. Unified ADC nonlinearityerror model for SAR ADC [ J]. Measurement,2008 (41 ):198 -204.
  • 9Krzanowska H, Szoltys M. Static integral nonlinearity model-ing and calibration of measured and synthetic pipeline analog-to-digital converters[ J]. IEEE Transactions on Instrumenta-tion & Measurement,2014,63(3) :502 -511.
  • 10Medawar S, Handel P,Bjorsell N, et al. Input - dependentintegral nonlinearity modeling for pipelined analog-digitalconverters [ J ]. IEEE Transactions on Instrumentation &Measurement ,2011, 60(10) :2609 -2620.

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