一种面向通信特征的3D NoC体系结构设计

A Communication Feature-Oriented 3D NoC Architecture Design

三维集成电路(three dimensional integrated circuit,3DIC)和片上网络(network on chip,NoC)是集成电路设计发展的两个趋势.将两者结合的三维片上网络(three dimensional networks on chip,3DNoC)是当前研究的热点之一.针对现有3DNoC的研究没有充分关注硅片内与硅片间的异构通信特征.提出了面向通信特征的硅片间单跳步(single hop inter dies,SHID)体系结构,该结构采用异构拓扑结构和硅片间扩展路由器(express inter dies router,EIDR).通过实验数据的分析表明,与3DMesh和NoC-Bus这两种已有的3DNoC结构相比,SHID结构有以下特点:1)延迟较低,4层堆叠时比3D-Mesh低15.1%,比NoC-Bus低11.5%;2)功耗与NoC-Bus相当,比3D-Mesh低10%左右;3)吞吐率随堆叠层数增加下降缓慢,16层堆叠时吞吐率比3D-Mesh高66.98%,比NoC-Bus高314.49%.SHID体系结构同时具备性能和可扩展性的优势,是未来3DNoC体系结构良好设计选择.

Three dimensional integrated circuits（3DIC）and networks on chip（NoC）are two trends of integrated circuit design.Three dimensional networks on chip（3DNoC）,which combines 3DIC and NoC,is one of the hot spots of current research.Existing 3D NoC researches paid inadequate attention to the feature of heterogeneous communication between inter and intra silicon wafer.This paper devises a kind of single hop inter dies（SHID）architecture which is a communication featureaware architecture using heterogeneous topology and express inter dies router（EIDR）.Analysis on the experimental data shows that compared with the existing 3DNoC structures of 3D-Mesh and NoCBus,SHID architecture has some characteristics：1）The latency of SHID architecture is smaller.It is15.1%less than 3D-Mesh and 11.5% less than NoC-Bus with stacking 4layers;2）The power consumption of SHID architecture equals NoC-Bus and it is 10% less than 3D-Mesh;3）The throughput of SHID architecture decreases more slowly as the number of stacked layers increases.It is 66.98%larger than that of 3D-Mesh and 314.49%larger than that of NoC-Bus with stacking 16 layers.SHID architecture has more advantages in terms of both performance and scalability and is a well design choice for future 3DNoC architecture.