期刊文献+

基于连续缓存和二级缓存的DFTL改进算法 被引量:5

An Improved DFTL Algorithm Based on Sequential Cache and Second Level Cache
下载PDF
导出
摘要 DFTL(demand-based FTL)是一种根据负载访问特点动态加载映射项到缓存中的知名FTL(flash translation layer)算法,但是它没有考虑到请求的空间局部性,而且缓存中的一个映射项剔除就可能会导致翻译页的更新,缓存中映射项的频繁剔除又会导致额外的擦除操作.在DFTL的基础上,提出了SDFTL(sequential/second cache DFTL)算法.SDFTL新设置连续缓存和二级缓存,连续缓存通过预取映射信息,利用请求的空间局部性,提高了FTL对连续负载的处理性能;二级缓存通过暂存从一级缓存中剔除的、发生更新的映射项,并采取批量更新策略回写到闪存,减少了闪存的翻译页写回次数和擦除次数.利用实际负载做的实验结果显示,SDFTL相比DFTL缓存命中率平均提高41.57%,擦除次数平均减少23.08%,响应时间平均减少17.74%. Flash translation layer(FTL)is one of the key techniques in solid state drive(SSD)design.Currently,demand-based FTL(DFTL)is a well-known FTL algorithm which can dynamically load map entries into cache based on the characteristics of requests.However,it does not consider the spatial locality of workloads,and one map entry evict out operation in cache may update one translation page;thus,frequent evict out operations will cause extra erase operations.Focusing on above drawbacks of DFTL,this paper proposes an FTL scheme called SDFTL(sequential/second cache DFTL),which sets a sequential cache and a second level cache additionally.The former improves the performance of FTL handling the workloads with high spatial locality by prefetching map entries to exploit the spatial locality of workloads.The latter is used to buffer the updated map entries,which are evicted from first level cache,to take advantage of batch updating strategy,and thus reduces the translation page write counts and erase counts.Experimental results of various realistic workloads show that SDFTL can improve the cache hit ratio by 41.57%and reduce the erase counts by 23.08%and response time by 17.74%compared with those of DFTL in average.
出处 《计算机研究与发展》 EI CSCD 北大核心 2014年第9期2012-2021,共10页 Journal of Computer Research and Development
基金 国家自然科学基金项目(61100044)
关键词 NAND闪存 固态硬盘 闪存转换层 二级缓存 空间局部性 NAND flash solid state drive flash translation layer second level cache spatial locality
  • 相关文献

参考文献18

  • 1陆游游,舒继武.闪存存储系统综述[J].计算机研究与发展,2013,50(1):49-59. 被引量:54
  • 2吴素贞,陈晓熹,毛波.GC-RAIS:一种基于垃圾回收感知的固态盘阵列[J].计算机研究与发展,2013,50(1):60-68. 被引量:9
  • 3Chang Y H, Hsieh J W, Kuo T W. Endurance enhancement of flash-memory storage, systems: An efficient static wear leveling design [C] //Proc of the 44th ACM/IEEE Design Automation Conf. Piseataway, NJ: IEEE, 2008: 212-217.
  • 4Wu G, Eckart B, He X. BPAC: An adaptive write buffer management scheme for flash-based Solid State Drives [C] // Proe of the 26th IEEE Syrup on Mass Storage Systems and Technologies (MSST'10). Piscataway, NJ: IEEE, 2010: 1-6.
  • 5赵鹏,白石.基于随机游走的大容量固态硬盘磨损均衡算法[J].计算机学报,2012,35(5):972-978. 被引量:10
  • 6Lee S, Lee B, Koh K, et al. A demand-based FTL scheme using dualistic approach on data blocks and translation blocks [C] //Proc of the 17th IEEE Int Conf on Embedded and Real Time Computing Systems and Applications (RTCSA). Los Alamitos, CA: IEEE Computer Society, 2011:167-176.
  • 7Lee S W, Park D J, Chung T S, et al. A log buffer based flash translation layet using fully associative sector translation [J]. ACM Trans on Embedded Computing Systems (TECS), 2007, 6(3) : 1-27.
  • 8Lee S, Shin D, Kim Y J, et al. LAST: Locality-aware sector translation for NAND flash memory-based storage systems [J]. ACM SIGOPS Operating Systems Review, 2008, 42 (6) : 36-42.
  • 9Jung D, Kang J U K, Jo H, et al. Superblock FTL: A superblock-based flash translation layer with a hybrid address translation scheme [J]. ACM Trans on Embedded Computing Systems (TECS), 2010, 9(4) : 1-41.
  • 10Gupta A, Kim Y, Urgaonkar B. DFTL: A flash translation layer employing demand-based selective of page level address mapping [C] //Proc of the 14th Int Conf on Architectural Support for Programming Languages and Opereating Systems (ASPLOS'09). New York: ACM, 2009:229-240.

二级参考文献75

  • 1Samsung Corporation. K9XXG08XXM Flash Memory Speci- fication. 2007.
  • 2Agrawal N, Prabhakaran V, Wobber T et al. Design tradeoffs for SSD performance//Proceedings of the USENIX 2008 Annual Technical Conference. Boston, USA, 2008: 57-70.
  • 3Gal E, Toledo S. Algorithms and data structures for flash memories. ACM Computing Surveys, 2005, 37(2): 163.
  • 4Ban A. Wear leveling of static areas in flash memory. US Patent App. 09/870, 315, Jun. 1 2001.
  • 5Woodhouse D. JFFS: The iournalling flash file system//Pro- eeedings of the Ottawa Linux Symposium. Ottawa, Canada, 2001.
  • 6Chang L. On efficient wear leveling for large-scale flash memory storage systems//Proceedings of the 2007 ACM symposium on Applied computing. Seoul, Korea, 2007: 1130.
  • 7Chang Y H, Hsieh J W, Kuo T W. Endurance enhancement of flash-memory storage systems: An efficient static wear leveling design//Proceedings of the 44th Annual Design Automation Conference. Berkeley, USA, 2007:217.
  • 8Spitzer F. Principles of Random Walk. Berlin: Springer Ver- lag, 2001.
  • 9Boyd J N, Raychowdhury P N. Biased Random Walks. Virginia Journal of Science, 1995, 46(1) : 35.
  • 10Kim J M, Noh S H et al. A space efficient flash translation layer for compact flash systems. IEEE Transactions on Consumer Electronics, 2002, 48(2): 366-375.

共引文献66

同被引文献17

引证文献5

二级引证文献11

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部