一种将测试集嵌入到Test-per-Clock位流中的方法

A New Method of Embedding Test Patterns into Test-per-Clock Bit Stream

集成电路测试方案的关键在于测试向量产生器的设计.传统的测试方法在测试向量生成、测试应用的过程中,没有充分利用测试数据位流来构建测试向量,从而造成了测试时间和存储开销的增加.为了减少测试成本,提出了一种基于test-per-clock模式的内建自测试方法.通过对线性移位测试结构的分析,提出了一种递进式的反复测试生成方法:顺序求解输入位流,逆向精简,多次求解以获得更优值,最终将测试集以较小的代价嵌入到test-per-clock位流中.在测试应用时,只需存储求解后的最小输入流,通过控制线性移位的首位从而生成所需的测试集.实验结果表明,在达到故障覆盖率要求的前提下,能显著地减少测试应用时间和存储面积开销.

The key of IC testing lies in the test patterns generator（TPG）design.Traditional testing methods do not make full use of the test data bit stream to construct test patterns during the test generation and application process,which results in high test cost due to the enormous test data.Test-per-scan scheme exposes the drawback of long test application time with the test data volumes increasing.In order to reduce the test cost,a built-in self test（BIST）scheme based on test-per-clock testing is proposed.Based on the analysis of linear shift test structure,a corresponding forwardbackward test patterns generation method is proposed,which efficiently embeds the test set into testper-clock bit stream.In this method,test patterns are determined by the solution of input-stream with fault dropping,where the input-stream is composed by the first bits of these patterns.The solved minimum input-stream after repeatedly reduction is directly stored in the memory to control the linear shifter in the test application,so as to generate the whole required test set.The experimental results demonstrate that the proposed method,under the precondition of meeting the required fault coverage,can obviously shorten test application time and reduce storage area overhead compared with other approaches.