摘要
针对白码查表法的储存器利用效率不高问题,给出了一种改进的基于非线性编码的算法和流水线结构,并通过VHDL语言编程,在FPGA上加以实现。仿真结果表明,与白码查表法的计算结果进行比较,非线性编码查表法提高了查表精确度,降低了查找表的大小,便于FPGA实现。
Aimed at low storage utilization efficiency of the general look-up table arithmetic, this paper presents an improved non-linear look-up table arithmetic and its pipeline structure, and implements this arithmetic on FPGA through in VHDL. Compared with the simulation results of general look-up table arithmetic, non-linear code look-up table improves the accuracy by non-linear coding , this improved arithmetic also reduces the look-up table size and its very suitable for FPGA chips to run.
出处
《数字通信》
2014年第4期19-23,共5页
Digital Communications and Networks
基金
重庆市自然科学基金(CSTC2010BB2415
CTSC2011jjA40006)
重庆市教委科学技术研究项目(KJ120501
KJ110530)
重庆市科委重点实验室专项经费
关键词
多天线
信号合并
相位加权值
非线性查表法
VHDL
multi-antenna, signal merger, phase weighted value, non-linear look-up table, VHDL