基于多因子CSE算法的AESS-盒电路优化设计

The Optimization Circuit Design of AES S-Box Based on a Multiple-Term Common Subexpression Elimination Algorithm

针对高级加密标准(AES)S-盒优化,提出了一种新的多因子公共项消除(CSE)优化算法.多因子CSE算法通过对组合逻辑表达式中所含因子最多的公共项优先消除,以简化逻辑表达式,从而有效地减少S-盒电路结构中的GF(2^4)域乘法逆电路和映射矩阵电路的面积和时延.结果表明,多因子CSE算法具有计算速度快,优化效率高的特点.优化后的S-盒组合逻辑电路采用0.18μm CMOS工艺,设计出的S-盒面积-延时积比目前最小面积和最短延时的S-盒组合逻辑电路分别减少了10.32%和19.64%.

Aiming at the optimization of advanced encryption standard （AES） S-box ,a novel multiple-term common subex-pression elimination （CSE ） algorithm was proposed .In order to simplify the combinational logic expressions ,the common subex-pressions containing the most factors took priority to be eliminated in the proposed approach ,thus effectively reduced the area and latency of the GF （2^4 ） multiplicative inverse circuit and the isomorphic mapping circuit in S-box .The results show that the multi-ple-term CSE algorithm achieves high computation and optimization efficiency .The optimized S-box is implemented in 0 .18μm CMOS technology .Compared with the smallest S-box and the shortest delay S-box in the existing work ,the optimized S-box saves about 10 .32% and 19 .64% of the area-delay product separately .