基于三模冗余结构的自刷新寄存器设计

Design of Self-reflesh Flip-flop Based on Triple Module Redundancy

设计了一种带自刷新功能的寄存器,该寄存器采用两级数据锁存结构,在第二级锁存结构中设计了一个选择电路。该选择电路采用三选二机制,用于三模冗余结构中取代常用寄存器,选择数据来自三模冗余结构的三路输出。有两路值相同,输出结果为该值,用于修正寄存器的输出值。在0.13μm工艺条件下用此结构设计的寄存器,面积为32.4μm×8.4μm,动态功耗0.072μW·MHz-1,建立时间0.1 ns,保持时间0.08 ns。该结构用于三模冗余结构中,可有效防止单粒子翻转效应(Single Event Upset,SEU)的发生。测试结果表明采用该结构的寄存器组成的存储单元三模冗余加固结构,在时钟频率1 GHz时,单粒子翻转错误率小于10-5。

Designed a self-reflesh flip-flop which structure has two data latches and a voter circuit is added to the second stage latch. The function of the voter is to output the logic value that corresponds to at least two of its inputs. The new flip-flop can be used to the circuit of triple module redundancy to instead of normal flip-flop. It fabricated in 0.13 pm standard CMOS process occupies a die area of 32.4μm×8.4μm, the dynamic power consumption was 0.072 4μW·MHz^-1, the setup time is 0.1 ns, and the hold time is 0.08 ns. This structure was applied to Triple Module Redundancy can efficiently prevent Single Event Upset, and Experiment results show that Single-Event Effect Error rate lower than 10^-5.