Cu/低k芯片铜引线键合中应力状态的数值分析

Numerical Analysis on the Stress Conditions of Cu /Low-k Chips in Thermosonic Cu Wire Bonding

新型Cu/低k芯片以其优异的性能逐步替代Al/SiO2芯片在微纳米器件中得到越来越多的应用。但由于其抗变形能力和强度较低,在引线键合中容易发生损坏。为研究Cu/低k芯片键合中的应力特征和失效机理,建立了Cu/低k芯片与传统Al/SiO2芯片铜引线键合过程的有限元分析模型,计算并对比分析了两种芯片中的应力状态。结果表明:芯片内应力在键合初期快速增长,随后继续增加,但增速变缓;键合过程中高应力区位于铜微球与芯片接触区边缘的下方,呈环形分布;振动中劈刀所在侧高应力区的范围及应力值明显大于另一侧;Cu/低k芯片中应力主要集中于Cu/低k层,Al/SiO2芯片中应力主要集中于劈刀所在侧的Si基板内。键合过程中应力在Cu/低k层的高度集中是新型芯片更易发生分层和开裂失效的根本原因。

The new Cu /low-k chips have been used more and more in micro and nano devices to replace traditional Al /SiO2 chips, for their excellent performances. Nevertheless, due to their low strength and resistance to deformation,failures of chips frequently happen during wire bonding. To study the characteristics of stress and the failure mechanisms,finite element models were developed to model the thermosonic Cu wire bonding process of the new Cu /low-k chips and the traditional Al /SiO2 chips.The results show that the stresses in the chip increase rapidly at the beginning stage,and then keep increasing at a lower rate. High stress region is located beneath the edge of contact interface between copper free air ball（ FAB） and bonding pad,and is in a ring form. The dimensions of high stress region and the stress are higher on the side where the capillary is located. For Cu /low-k chips,stress is mainly concentrated within the Cu /low-k layer,while it is mainly concentrated in the Si substrate on the side where the capillary is located for Al /SiO2 chips. The highly concentrated stress in Cu /low-k layer is the essential causes of delamination and cracking in new Cu /low-k chips.