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基于M4结构的混合逻辑全加器设计

Full adder design based on hybrid logic of M4 structure
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摘要 针对全加器速度和功耗日益突出的矛盾,提出一种基于M4结构的混合逻辑全加器(HLM4-FA)设计方案.通过两个独立的部分分别产生输出信号,减小电路模块间内部信号的输出负载,优化器件的延时.针对不同的模块,采用混合逻辑设计方法,克服单一逻辑设计电路的局限性,降低电路的功耗,从而降低全加器的功耗延时积.与Hybird、Hybird_CMOS和SR_CPL_Buffer全加器相比,延时和功耗延时积减小分别达33%和37%,有效节省了电路能耗. Against the increasing contradiction between speed and power consumption of full adders, a new full ad-der design method based on hybrid logic of M4 structure （ HLM4-FA） is proposed. By generating output signals with two separate parts, the output load of internal signals between different modules is reduced, and the delay is optimized. The employment of hybrid logic styles for different modules in the design improves the speed, lowers the power consumption,and also reduces the power delay product （ PDP） . Compared with the Hybird, Hybird_CMOS, and SR_CPL_Buffer full adders,the proposed full adder reduces the delay and PDP by 33% and 37% respectively.
作者 夏银水 王士恒 钱利波
机构地区 宁波大学信息科学与工程学院
出处 《深圳大学学报（理工版）》 EI CAS 北大核心 2014年第5期479-486,共8页 Journal of Shenzhen University(Science and Engineering)
基金 国家自然科学基金资助项目(61131001)~~
关键词 集成电路技术 全加器 运算电路 混合逻辑 低能耗 延时 功耗延时积 integrated circuit full adder arithmetic circuit hybrid logic low energy consumption delay power delay product
分类号 TN4 [电子电信—微电子学与固体电子学]
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参考文献18

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深圳大学学报（理工版）
2014年 第5期

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