一种应用于流水线ADC数字校准算法及实现

A Digital Calibration Algorithm and the Implantation in Pipeline ADC

数字校准技术是实现高性能流水线模数转换器(ADC)的关键技术之一。文中对流水线ADC结构进行了分析,研究了误差来源,提出了一种数字校准方案。该方案采用有限状态机的方法实现,运用Verilog HDL语言完成了电路硬件描述,并完成了物理实现,在功能和时序上实现了内部电路协调高效地工作。该算法适用于每级1.5 bit和多bit的子级转换电路。实现结果表明:用该硬件实现方法设计的数字校准系统能够有效地校准电容失配引起的误差,电路实现简单,可靠性好,对模拟电路的改动较小,满足高性能ADC的要求。

Digital calibration technology is one of a key technologies in high performance pipeline ADC. The structure of the pipeline ADC is analysed in this paper,and the source of the errors is researched, a suggestion of the digital calibration is offered. Finite state machine is used to implant the plan proposed in the paper, and Verilog HDL is used for hardware implantation and the physical design is accomplished. Internal circuits work high effectively and harmoniously in timing. The calibration algorithm is suitable for 1.5 bit/stage and multi-bits/stage. Experimental results indicated that the hardware implantation method of the digital calibration circuit can effectively calibrate the errors caused by the capacity mismatch, the circuit implantation is simple, good reliability, less change the analog circuits, and meet the demands of the high performance ADC converter.