一种可扩展高速FPGA嵌入式ECC电路设计

A Extensible and High Speed FPGA Embedded ECC Circuit Design

针对当前现场可编程门阵列(FPGA)嵌入式帧检错与纠错(ECC)电路速度低、可扩展性差的不足,设计了一种新型可扩展的高速流水线型帧ECC电路.它充分利用FPGA回读数据的特征,在FPGA回读数据的同时完成单帧数据的ECC校验,不占用额外的存储资源.每一级流水线的延时相对于整个FPGA配置电路的延时而言是非常小的,不会影响到整个FPGA配置电路的速度.实验结果表明,和Xilinx设计的ECC电路相比,本设计的平均最高工作频率是其1.5倍,平均资源占用率仅为其10%.此外,该帧ECC电路具有良好的扩展性,通过调整流水线的级数就能够很好地适应FPGA配置位流结构的改变.

Due to the low speed and poor scalability of the FPGA embedded ECC circuit,this paper presents a novel pipelined frame ECC circuit with high performance and good scalability.It takes full advantage of the feature of the readback data from FPGA array,it can complete the ECC check for a single frame of data without any additional storage resources while reading back the data.The delay of each pipeline is very small relative to the entire FPGA configuration circuit,so it will not affect the speed of the FPGA configuration circuit.The experimental results show that the pipelined ECC circuit can improve the speed by 50%,and reduce the resource utilization by 90%against the ECC circuit of Xilinx.What＇s more,this circuit shows a high flexibility,when the structure of the FPGA configuration bitstream changes,changing the pipeline stages will fit it.