期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

一种具有2-bit/cycle结构的400-MS/s 8-bit逐次逼近型模数转换器设计

A 400-MS/s 8-bit SAR ADC with 2-bit/cycle
原文传递
导出
摘要 设计了一种高速的逐次逼近型模数转换器(Successive Approximated Register Analog-Digital Converter,SAR ADC),与传统SAR ADC相比,该ADC除了采样电容阵列,额外使用了一个辅助数模转换器(Auxiliary Digital-Analog Converter,AUX-DAC)来实现2-bit/cycle.系统设计的SAR ADC使用了一个共享的内插预放大器,可以将输入信号和比较器隔离开,减小了比较器的回踢噪声.为了进一步提高转换速度,采用比较器交替工作模式,其输出结果直接送给电容阵列进行处理,与传统SAR ADC相比大大减小了逻辑延时.由于架构中使用了多路比较器,因此采用前台校准技术用来校正比较器的失调电压.后仿结果表明该ADC在400M采样速率和1.2V的电源电压下,可以实现48dB的SNDR,功耗为5.6mW,优值FoM为67fJ/conversion-step. A 400-MS/s 8-bit SAR ADC with 2-bit/cycle conversion is presented here.Compared with conventional SAR structure,an AUX-DAC is proposed to achieve high switch energy efficiency and low power.The proposed structure of ADC uses a shared interpolator,which not only reduces one DAC,but also separates the input signal from the comparator to reduce the kickback noise.To further increase the speed,the logic delay is reduced by the comparators working alternatively and the results directly sent to the M-DAC.Foreground calibration is used to calibrate the offset of the comparators.The post simulation results show that the ADC achieves a SNDR of 48 dB,power consumption of 5.6mW and FoM of 67fJ/conversion-step at 400MS/s rate with 1.2Vsupply voltage.
作者 代国宪 陈迟晓 叶凡 任俊彦
机构地区 复旦大学专用集成电路与系统国家重点实验室
出处 《复旦学报（自然科学版）》 CAS CSCD 北大核心 2014年第4期446-451,F0002,共7页 Journal of Fudan University：Natural Science
基金 国家高技术研究发展计划(863计划)(2013AA014101)资助项目
关键词 2-bit/cycle SAR ADC 内插预放大器 交替工作比较器 前台校准 2-bit/cycle SAR ADC interpolator alternative comparators foreground calibration
分类号 TN432 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献8

  • 1Akita I, Furuta M, Matsuno J, et al. A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track- and,hold amplifier[C] // solid State Circuits Conference (A-SSCC), 2011 IEEE Asian. Jeju, Korea: IEEE PRESS, 2011: 14-16.
  • 2Tao J, Wing L, Zhong C, et al. Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR- ADC in 40nm-CMOS[C]//Custom Integrated Circuits Conference (CICC). San Jose, CA, USA: IEEE PRESS, 2010: 19-22.
  • 3Yamase T, Uchida H, Noguchi H. A 22-roW 7 b 1. 3-GS/s pipeline ADC with 1-bit/stage folding converter architecture[C]//VLSI Circuits (VLSIC), 2011 Symposium on. Kyoto, Japan: IEEE PRESS, 2011 : 15-17.
  • 4Liu W B, Chang Y C, Hsien S K, etal. A 600 MS/s 30 mW 0. 13 txm CMOS ADC array achieving over 60 dB SFDR with adaptive digital equalization[C] // Solid-State Circuits Conference-Digest of Technical Papers, ISSCC 2009. IEEE International. San Francisco, USA: IEEE PRESS, 2009: 8-12.
  • 5Cao Z H, Yan S L, li Y C. A 32 mW 1.25 GS/s 6 b 2 b/step SAR ADC in 0. 13 μm CMOS[C]//SOlid- State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International. San Francisco, USA: IEEE PRESS, 2008: 3-7.
  • 6Liu C C, Huang Y T, Huang G Y, et al. A 6-bit 220-MS/s time-interleaving SAR ADC in 0. 18μm digital CMOS process [C] // VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on. Hawaii USA: IEEE PRESS, 2009: 28-30.
  • 7Hong H K, KimW, Park S J, etal. A 7 h 1 GS/s 7. 2 mW nonbinary 2 b/cycle SAR ADC with register- to-DAC direct control[C]//Custom Integrated Circuits Conference(CICC), IEEE. San Jose, CA', USA: IEEE PRESS, 2012: 9-12.
  • 8Lee H, Masaya M, Akira M. A 6-hit subranging ADC with single CDAC interpolation[C] /// Electron Devices and Solid-State Cireuits(EDSSC), 2013 IEEE International Conference of. Hong Kong: IEEE PRESS, 2013: 3-5.
复旦学报（自然科学版）
2014年 第4期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部