摘要
针对无线通信中低功耗维特比译码器设计结构复杂的问题,提出一种四级流水串并结合的(2,1,9)低功耗维特比译码器。该译码器采用改进的加-比-选(ACS)单元,以降低硬件复杂度,在提高时钟运行速率的基础上减少运行功耗。幸存路径存储单元采用改进的路径相消方法,减少译码器的输出延迟,提高译码效率。性能分析结果表明,基于TSMC 0.18μm CMOS逻辑工艺,在1.62V,125℃操作环境下,该译码器数据最大速度为50MHz,自动布局布线后的译码器芯片面积约为0.212mm2,功耗约为23.9mW。
Toward the complicated structure of low power implementation of the Viterbi decoder in wireless communication,a low power （2,1,9） Viterbi decoder with the structure of series and parallel combination in four-level pipeline is proposed in the paper. To increase working rate, with the consideration of the implementation hardware complexity,a modified Add-compare-select（ ACS） unit is used to satisfy its low power decoding requirment. In order to increase the efficiency of decoding and decrease the latency of decoder,a method of path mutual eliminating is employed in the design. Implemented by TSMC 0. 18 μm standard CMOS technology under 1. 62 V and 125 ℃,and analysed with placement and route,the chip’ s highest speed is about 50 MHz,the area is 0. 212 mm2 ,and the power comsumption is 23. 9 mW.
出处
《计算机工程》
CAS
CSCD
2014年第10期114-117,共4页
Computer Engineering
基金
湖南省科技计划基金资助项目(2012GK3151)
关键词
维特比译码器
低功耗
加-比-选
路径度量存储
路径相消
幸存路径
Viterbi decoder
low power
Add-compare-select （ ACS ）
path metric memory
path mutual eliminating
survivor path
