全数字接收机中的并行插值技术研究

The Research of Parallel Interpolation in All Digital Receiver

文章针对全数字接收机提出了一种并行插值结构。它不同于以往的串行插值,一次可以计算出一个符号内所需的所有插值点。这个特点改善了硬件中对插值计算的速度限制,提升了全数字接收机的性能。同时仿真结果表明,该并行插值结构可以很好的调整定时误差,适合应用在高速率的数据通信中。

We propose a structure of parallel interpolation for all-digital receiver, which is different from serial interpolation. It can calculate all interpolators in one symbol once. Because of it, the limit of processing rate is broken through and the performance of all-digital receiver is improved. Simulation demonstrates that the structure of parallel interpolation makes timing adjustment very well and adapts to the high data rate communications.