期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

层次化片上多核处理器性能研究

Performance analysis of hierarchical chip multicore processor
下载PDF
导出
摘要 层次化片上多核处理器紧耦合多个处理核构成"簇节点",对访存和片上通信的局部性有良好支撑,能有效地缓解片上多核间数据通信带来的通信开销。文章通过构建精细的层次化片上多核处理器仿真器,利用随机任务模型研究"簇节点"大小对系统性能的影响。仿真发现,一定系统规模下,要获得良好的系统性能,层次化片上多核处理器需要在"簇节点"数目与"簇节点"的大小(节点内处理核的数目)之间仔细权衡。 Hierarchical chip multicore processor（HCMP） can well support the memory access and on-chip communication locality through cluster node ,each of w hich consists of several tightly coupled processing cores ,thus efficiently reducing the data communication latency .In this paper ,a C＋ ＋based cycle-accurate simulation model is established ,and the influence of processing core number in each cluster node on HCMP performance is studied by using stochastic task model .The simulation re-sults show that under certain system scope ,in order to achieve high performance of HCM P ,the con-figuration of the cluster node number and processing core number in each cluster node should be care-fully considered .
作者 侯宁 赵红梅 宋宇鲲
机构地区 河南城建学院电气与信息工程系 合肥工业大学微电子设计研究所
出处 《合肥工业大学学报（自然科学版）》 CAS CSCD 北大核心 2014年第10期1226-1230,共5页 Journal of Hefei University of Technology：Natural Science
基金 国家自然科学基金资助项目(61179036 61106020)
关键词 层次化结构 片上多核处理器 建模 性能分析 hierarchy architecture chip multicore processor modeling performance analysis
分类号 TP302 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献12

  • 1Edwards B, Amann J, Conlin R, et al. TILE64-Processor: a 64-core soc with mesh interconnect[C]//IEEE Internation- al Solid-State Circuits Conference ( ISSCC : 08 ), 2008 : 588-589.
  • 2Waingold E, Taylor M, Srikrishna D, et al. Baring it all to software: raw machines[J]. IEEE Computer, 1997,30(9) : 86-93.
  • 3Butts M,Budlong B, Wasson P, et al. Reconfigurable work farms on a massively parallel processor array[C]//16tb. Irt- ternational Symposium on Field-Programmable Custom Computing Machines (FCCM'08), 2008: 206-218.
  • 4Balfour J, Dally W J. Design tradeoffs for tiled CMP on- chip networks[C]//Proc of the 20th Annual Int Conf on Supercomputing ( ICS ' 06 ). New York: ACM, 2006: 187-198.
  • 5Horwitz M, Dally W. How scaling will change processor ar- chitecture [C]//Proc of IEEE Int Solid-State Circuits Conf (ISSCC'04). Piscataway, NJ: IEEE, 2004 ; 132- 133.
  • 6欧阳一鸣,黄河,梁华国.功耗优先的NoC通讯架构测试方法[J].合肥工业大学学报（自然科学版）,2010,33(10):1510-1514. 被引量：5
  • 7Raghunathan V, Srivastava M B, Gupta R K. A survey of techniques for energy efficient on-chip communication[C]// Proc of the 40th Annual Design Automation Conf (DAC' 03). New York: ACM,2003: 900-905.
  • 8ITRS 2011. International technology roadmap for semicon- ductors[EB/OL]. [2013-11-23]. http://www, irts. net.
  • 9Das R,Eachempati S,Mishra A K,et al. Design and evalua- tion of a hierarchical on-chlp interconnect for next genera- tion CMPs[C]//Proc of IEEE 15th Int Symp on High Per- formance Computer Architecture (HPCA'09). Los Almi- tos, CA: IEEE Computer Society, 2009:175-186.
  • 10Bourduas S, Zilic Z. A hybrid finN/mesh interconnect of network-on-chip using hierarchical tings for global routing [C]//First International Symposium on Network-on-chip (N07), USA, 2007 : 195-204.

二级参考文献30

  • 1Petersen K,Oberg J.Toward a scalable test methodology for 2D—mesh network-on-chips[C] //Design Automation and Test in Europe (DATE).Nice,France,2007:367—372.
  • 2Raik J,Govind V,Ubar R.An external test approach for network-on-a-chip switches[C] //15th Asian Test Symposium (ATS).Fukuoka,Japan,2006:437—442.
  • 3Hosseinabady M,Banaiyan A,Bojnordi M N,et al.A concurrent testing method for NoC switches[C] //Design Automation and Test in Europe(DATE).Munich,Germany,2006:1171—1176.
  • 4Cota E,Liu C.Constraint-driven test scheduling for NoC-based systems[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2006,25(11):2465—2478.
  • 5Sedghi M,Koopahi E,Alaghi A,et al.An exhaustive test strategy based on flooding routing for NoC switch testing[C] //IEEE East-West Design and Test Symposium (EWDTS).Yerevan,Armenia,2007:262—267.
  • 6Sedghi M,Koopahi E,Alaghi A,et al.An NoC test strategy based on flooding with power,test time and coverage considerations[C] //VLSID 2008,21st International Conference.Hyderabad,India,2008:409—414.
  • 7Guindani G,Reinbrecht C,Raupp T,et al.NoC power estimation at the RTL abstraction level[C] //IEEE Computer Society Annual Symposium on VLSI.Montpellier,France,2008:475—478.
  • 8Wu Ning,Ge Fen,Wang Qi.Simulation and performance analysis of network on chip architectures using OPNET[C] //7th International Conference on ASIC.Guilin,China,2007:1285—1288.
  • 9Hu J,Marculescu R.Energy-and performance-aware mapping for regular NoC architectures[J].IEEE Transactions on Computer-Aided Design of Ics and Systems,2005,24(4):551—562.
  • 10Agarwal A. Tiled multicore processors: The four stages of reality [keynote][C] //Proc of the 40th Annual IEEE/ACM Int Symp on Microarchitecture (MICRO'07). Los Alamitos, CA: IEEE Computer Society, 2008.

共引文献10

合肥工业大学学报（自然科学版）
2014年 第10期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部