基于SDH仿真平台的时钟成环规避方法研究

SDH环网中网元间配置双向线路时钟源时,容易出现时钟成环问题。针对该问题,本文提出一种基于破坏时钟成环条件原则的时钟源配置规则。对于环网中配置有环外时钟源的网元,通过配置一个线路时钟源或不配置线路时钟源的方式,来避免时钟成环条件的成立,从而避免环路中时钟成环的出现。并在SDH仿真平台上对单环网络以及多环网络的时钟配置进行分析,验证了规则的有效性。

The SDH ring network is prone to appear clock loop when the NEs configure bidirectional line clock sources. For this problem, the paper proposes a clock configuration rule based on the principle of destruction the condition of clock loop. When we configure clock sources to the SDH network, we configure one or zero line clock source to the NEs which configured external clock source in the network. In this way, the SDH network can avoid the establishment of condition of clock loop, thus the network can avoid clock loop. Then we verifies the effectiveness of the rule through analyzing the clock configuration in single-loop and multiloops networks on the SDH simulation platform.