三维扫描树叶子节点和TSVs数量的优化方法

Optimizing the number of leaf nodes and TSVs in three dimensional scan tree

扫描树结构能够有效地减少集成电路的测试数据量和测试时间,降低电路的测试成本.为减少三维电路中扫描树的叶子节点和硅通孔数量,首先得出了扫描树中叶子节点的最小数量为最大相容组中所含扫描单元数量的结论,然后进一步得到了叶子节点取得最小值的充分必要条件.并在此基础上,提出了一种启发式算法来确定扫描树中相容组的连接顺序,使得叶子节点数量取得最小值的同时能够优化硅通孔的数量.实验结果表明了所提方法的有效性.

Scan tree architecture can effectively reduce test data volume, test time and test cost for integrated circuits. To reduce the number of leaf nodes and TSVs（through silicon vias） in scan tree for three dimensional integrated circuits, this paper firstly draws the conclusion that the minimum number of leaf nodes is the number of scan cells contained in the maximal compatible group. Then, the necessary and sufficient condition achieving the minimum number of leaf nodes is presented. On the basis above, a heuristic algorithm is proposed, which can minimize the number of leaf nodes and reduce consumed TSVs as many as possible. Experimental results demonstrate the effectiveness of the proposed technique.