高压断路器分-合能力合成回路试验模拟系统设计

Design of Simulation System of the Synthesis Loop for Testing the Closing Capacity of High Voltage Breaker

为在试验室条件下进行小容量的合成试验以节省调试同步控制系统的成本及方便调试同步控制系统,设计了一种合成回路试验的模拟系统。首先,在分析威尔合成试验和高压关合试验原理的基础上,计算主回路各个部分所采用的元件参数。然后根据合成试验的工作特点,设计试验回路的控制系统。利用单片机进行时序控制,得到符合要求的模拟系统。通过与同步控制系统的联调,得到电压回路的触发时间的误差<50μs,延弧回路的触发时间误差<40μs,可以保证合成试验的等效性,证明提出的模拟系统的可行性。

To conduct small-capacity synthesis tests in laboratory, to save the cost of synthesis tests for debugging syn-chronous control system, and to make the debugging of synchronous control system convenient, we developed a set ofsimulation system for synthesis loop tests. Firstly, on the basis of analyzing Wiel test and high-voltage closing test, wecalculated the component parameters for the main circuit of the simulation system. Secondly, according to the workingcharacteristics of synthesis tests, we designed a control system of the simulation system. The simulation system uses SCMfor time sequence control and meets the requirements of its design. According to the cooperation tests with the synchron-ous control system, it is obtained that the error of the actual trigger time is smaller than 501xs, and the error of the pro-longarc circuit is smaller than 40 Ixs, which ensures the equivalence of synthetic test and proves the feasibility of the proposedsimulation system.