摘要
针对VSP系统对测井数据并行采集的要求,采用FPGA作为核心控制器,结合ADS1252模数转换芯片、SDRAM存储芯片和RS485通信技术构建了多路数据采集系统。利用Verilog编写有限状态机实现FPGA控制多路ADC并行采集和SDRAM的存储操作,并能够对多路数据并行采集和正确存储,使系统具有实时性强、电路简单、干扰噪声低等优点。通过signaltap对该系统的采集和存储效果进行在线测试,并结合matlab仿真对比分析,验证了系统的可靠性和准确性。
According to the requirements of VSP system parallel acquisition for logging data,we combined ADS1252 modulus conversion chip,SDRAM memory chips and RS485 communication technology to build a multi-channel data acquisition system with FPGA in Cyclone IV series as its core controller.In this system,we used Verilog write finite state machine,which helps to achieve FPGA controlling multi-channel ADC parallel acquisition and SDRAM store operation and be able to perform parallel acquisition and accurate storage of multi-channel data,thus equipping the system with strong real-time performance,simple circuit,low noise interference and other advantages.By online testing on the collection and storage properties of the system through signaltap and comparative analysis with matlab simulation,the reliability and accuracy of the system is verified.
出处
《核电子学与探测技术》
CAS
CSCD
北大核心
2014年第5期622-626,共5页
Nuclear Electronics & Detection Technology
基金
国家自然科学基金重大科研仪器设备研制专项(41227802)
国家自然科学基金(41274109)
国家杰出青年科学基金(41025015)
四川省青年科技创新研究团队项目(2011JTD0013)
四川省科技支撑计划(2013FZ0022)