一种基于零点优化的低功耗ΣΔ调制器

A low power ΣΔ modulator based on zero optimization

设计了一种基于零点优化的低功耗ΣΔ调制器,该结构不需要传统ΣΔ调制器中的数字抵消逻辑部分,可以采用低增益的运算放大器(OTA),减小了设计难度。此外,设计的调制器中积分器的输出摆幅大大减小,积分器的非理想特性得到了抑制。通过优化零点位置,增加了调制器的稳定性和动态范围,信噪比和未进行零点优化相比得到了大大提高。设计的调制器采用0.35μm CMOS工艺仿真实现,仿真结果表明,在带宽为500 kHz、过采样为16 Mb/s时,信噪比达到90.9 dB,功耗仅为3.78 mW。

In this paper, a novel wideband,low power multi-loop modulator is proposed. It is insensitive to low gain operation amplifier（OTA） while all the digital cancelled logic is removed. The effect of non-idealities in amplifiers can be suppressed as the low-distortion reduced the signal swing. Local feedback is used to achieve optimal zero placements. Using this technique can improve the overall SNDR by 10 dB at an over sampling ratio（OSR） of 16 Mb/s. The modulator is implemented in a 0.35 μm CMOS technology. Simulation results show that 90.9 dB SNDR is achieved, when it is clocked at 16 MHz sampling rate and at an over sampling ratio of 16 Mb/s.With 3.3 V power supply, the power dissipation is 3.78 mW.