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一种对失调和电容失配误差进行补偿的流水线ADC子级电路 被引量：4

A Sub-Stage Circuit with Comparator Offset and Capacitor Mismatches Errors Compensating for High Speed Pipelined ADC
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摘要 设计一种用于高速高精度流水线ADC的流水线ADC子级电路,采用伪随机序列控制子ADC电路中比较器阵列的参考比较电压。比较器的高低位被随机分配,消除某个比较器的固有失调对子ADC量化的影响,温度计码的伪随机性可以消除MDAC电容的失配误差对余量输出的影响。电路采用0.18μm 1P5M 1.8 V CMOS工艺,运用于12 bit 250 Msample/s流水线ADC电路中,实际测得流水线ADC电路的SNR为69.92 dB,SFDR为81.17 dB。 A sub-circuit for high-speed, high-resolution pipelined ADC is presented. Reference voltages in comparators array are controlled by pseudorandom sequences. MSBs and LSBs of comparators are assigned randomly, accordingly the effect of offset of some comparator on ADC quantization is eliminated. Pseudo-random thermometer code cancels the effect of the mismatches of MDAC capacitors on residue output. This circuit implemented in 0.18 μm 1PSM 1.8 V CMOS process is applied to a 12-bit 250 Msample/s pipelined ADC. Test results shows that the ADC has an SNR of 69.92dB and an SFDR of 81.17 dB
作者 戴强 薛颜 杨霄垒 周启才 吴俊 郭良权
机构地区 中国电子科技集团第五十八研究所 江南大学物联网工程学院
出处 《电子器件》 CAS 北大核心 2014年第5期812-815,共4页 Chinese Journal of Electron Devices
关键词 流水线模数转换器 伪随机序列 失调误差 电容失配误差 pipelined analog-to-digital converter pseudo-random sequence offset voltage mismatches of capacitor
分类号 TN405 [电子电信—微电子学与固体电子学]
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参考文献8

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二级参考文献9

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共引文献5

同被引文献22

  • 1张杨,诸昌钤,何太军.图形硬件通用计算技术的应用研究[J].计算机应用,2005,25(9):2192-2195. 被引量：6
  • 2彭新芒,杨银堂,朱樟明.一种采用0.5μm CMOS工艺的多通道SAR ADC[J].微电子学,2007,37(2):217-220. 被引量：2
  • 3Lee S C,Jeon Y D, Kwon J K,et al. A lO-bit 205-MS/s 1.0-mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications [J]. IEEE Journal of Solid-State Circuits, 2008,42 (12) :2688- 2695.
  • 4Huang G Y, Chang S J, Liu C C, et al. 10-bit 30-MS/s SAR ADC Using a Switchback Switching Method [J]. IEEE Transactions on Very Large Scale Integration Systems, 2013,21 (3) : 584-588.
  • 5Harpe P, Cantatore E, Van Roermund A. A 10b/12b 40 kS/s SARADC With Data-Driven Noise Reduction Achieving up to lO.lb ENOB at 2.2 fJ/Conversion-Step [J]. IEEE Journal of Solid-State Circuits, 2013,48(12) : 3011-3018.
  • 6Hu W,Liu Y T,Nguyen T,et al. An 8-Bit Single-Ended Ultra-Low- Power SAR ADC with a Novel DAC Switching Method and a Coun- ter- Based Digital Control Circuitry [J]. IEEE Transactions on Cir- cuits & Systems I Regular Papers,2013,60(7) : 1726 - 1739.
  • 7Shafti A, Yavari M. A Zero-Crossing Based 10-bit 100 MS/s Pipe- line ADC with Controlled Current in 9002nm CMOS [J]. Analog Integrated Circuits & Signal Processing, 2014,80( 1 ) : 141-151.
  • 8Verbruggen B, Iriguchi M, Craninckx J. A 1.7 mW 1 lb 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS [J]. IEEE Journal of Solid-State Circuits, 2012,47 (12) :2880-2887.
  • 9刘金娟,张东晨,巩天宁,李涛.流水线技术及并行计算在GPU中的应用分析[J].软件导刊,2008,7(9):25-26. 被引量：2
  • 10林俪,任俊彦,叶凡.A 1.4-V 25-mW 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS[J].Journal of Semiconductors,2010,31(2):70-75. 被引量：1

引证文献4

二级引证文献6

电子器件
2014年 第5期

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