基于SW-Log-MAP算法的Turbo-SISO译码器的设计与实现

The design and implementation of SW-Log-MAP decoder used for Turbo-SISO

Turbo码通过软输入、软输出(SISO)的迭代译码达到了接近Shannon理论极限的性能,为了改进其译码延时较大的缺点,设计了一种可单芯片实现的、支持Turbo译码的滑动窗LogMAP译码器(SW-MAP),并在Xilinx Veritex-4 FPGA上用Verilog HDL语言进行了仿真。结果表明,使用该译码器对CCSDS标准Turbo码译码,可以达到10 Mbit·s-1的数据处理速率,且与软件仿真相比性能损失在0.1 d B以内。

Turbo code adopting iterative decoding of SISO reaches the performance near to Shannon limit. In order to correct the weakness of long-time decoding delay, SW-MAP which achieves a single chip that supports Turbo code is designed and it is implemented on Xilinx Veritex-4 FPGA with Verilog HDL language. The results show that date process rate can reach 10 Mbit · s^ -1 using this SW-MAP to de- code Turbo code based on CCSDS standard and performance loss is within 0. 1 dB compared with software simulation.