互连线对CMOS电路性能的仿真分析

Analyzing influence of interconnect on performance for CMOS circuits

随着芯片集成规模的不断扩大及信号频率的不断提高,互连寄生成为限制芯片性能的关键因素之一。应用通用的互连线等效RLC模型,采用Advanced Design System(ADS)和SPICE软件首先分析了频率及互连线长度对信号传输特性的影响。在此基础上,又分析了互连线对环形振荡器及传输门两种CMOS电路性能的影响。结果表明,高频及较长的互连线更容易导致信号质量的恶化,包括幅值的衰减及相移的产生。而且,在尺寸小于0.25μm的工艺条件下,互连线明显恶化了电路性能,说明在更微小尺寸的工艺下,在电路设计仿真时要考虑互连线的寄生效应。

The electrical interconnect has become one of the key factors limiting the circuit perform- ance of chips, with the continuous expansion and operating frequency integrated chip scaling of VLSI technology unceasing enhancement. The general interconnect RLC equivalent circuit model was adopted for analyzing the effect of frequency and interconnect length on the signal performance using Advanced Design System （ADS） and SPICE software. Moreover, the effect of interconnects on the CMOS circuits also was discussed, such as a ring oscillator and a transmission gate. The simulated results show that the parasitic effects of interconnects have seriously irLfluenced the performance of CMOS IC, including the amplitude attenuation and phase shift. Under the conditions of size less than 0.25 μm, the circuit per- formance interconnect was worsened significantly by interconnect. It means that the interconnect parasitic effects is very necessary when the ciruit simulation accured under the process of more small size.