期刊文献+

铜柱互连技术专利衍进分析

Analysis of patent evolution of Cu pillar bump technology
原文传递
导出
摘要 铜柱互连技术被越来越多地应用于电子器件的先进封装中,铜柱互连技术已成为倒装芯片封装的主流。综述了该技术的发展历程并对铜柱互连技术的重要专利进行较详细的分析,给出了该技术的发展脉络及未来可能的发展方向,为后续的研究提供参考。 Cu pillar bump technology is increasingly applied in advanced IC packages. Cu pillar bump technology becomes mainstream technology for the flip chip assembly technologies. The development course about Cu pillar bump technology is reviewed and important patents about this technology are analyzed in detail. The development course and future possible development direction about this technology are obtained to hope establishing a base for follow-up studies.
出处 《电子元件与材料》 CAS CSCD 北大核心 2014年第11期10-13,共4页 Electronic Components And Materials
关键词 铜柱 电子封装 综述 互连 专利 专利分析 Cu pillar electronic package review interconnect patent patent analysis
  • 相关文献

参考文献12

  • 1精工.Copperpillartinbumponsemiconductorchip:Japan,JPS5632748A[P],1979-08-24.
  • 2夏普.Resinsealsemiconductorpackageandmanufacturingmethodofthesame:Japan,JPS59143343A[P],1983-02-04.
  • 3东芝.Semiconductorpackagesubstrateshavinglayeredcircuitsegments,andrelatedmethods:Japan,JPS60217646A[P],1984-04-13.
  • 4Fujitsu. Wire interconnect structures for connectin an integrated circuit to a substrate : USA, US5334804A [P], 1992-11-17.
  • 5LAU J H. Flip chip technologies [M]. USA: McGraw-Hill Companies, 1995: 367-369.
  • 6LSI. Process for making all interconnect bump tbr flip-chip integrated circuit: USA, US546635A [P]. 1994-06-02.
  • 7IBM. Chip having a metal pillar structure: USA, US6229220131 [P]. 1996-09-11.
  • 8INTEL. Method for preparing a conductive pad, US7276801B2 [P]. 2010-11-04.
  • 9台积电.一种集成电路元件:中国,CNl02024769B[P],2010-02-24.
  • 10台积电.大尺寸投射电容式触摸屏的扫描装置:中国,CNl02064154B[P],2010-09-24.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部