一种适用于频率变化的单相数字锁相环

Novel Single-phase Digital Phase-locked Loop Considering Frequency Variation

基于传统的单相电网电压相位检测方法在频率变化时存在的缺陷,提出了一种新型的数字锁相环设计方法。所提出的数字锁相环通过带遗忘因子的递推最小二乘法进行椭圆拟合辨识出椭圆参数,应用锁相环产生不对称相位输出,消除电网频率变化时鉴相输出的2倍频分量。推导出不对称相位和椭圆参数的关系,设计带遗忘因子的递推最小二乘法,最后给出仿真和实验结果,仿真和实验结果验证了该方法的准确性。

When the frequency is varied,the dynamic behavior of traditional phase-locked loop system becomesdiscontented,a novel digital phase - locked loop（DPLL）was put forward. In the new DPLL presented,ellipseparameters were identified by recursive least square method based on forgetting factor and asymmetric phase output ofDPLL produced with identified parameters by which the second harmonic was eliminated in frequency variation. Therelationship between asymmetric phase and ellipse parameters was derived and RLS method based on forgetting factorwas designed,simulation and experiment results validate the theoretical analysis.