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一种基于电容匹配算法的低噪声SAR ADC设计 被引量：2

Design of a Low Noise SAR ADC Based on Capacitor Match Algorithm
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摘要 设计了一个12位,采样速率为120kS/s的SAR ADC。提出了一种12位精度下,能在电容面积和精度之间进行折中的算法,使得电容的整体面积、速度和功耗达到优化。通过对比较器的设计,解决了在噪声环境下,影响比较器性能的电荷注入、带宽、转换速度等问题。在0.35μm2P5MCMOS工艺下进行了流片,测试结果表明,设计的SAR ADC的DNL和INL均小于±1LSB,功耗为1.5mW。 A 12-bit 120 kS/s SAR ADC was designed with a trade off between the area and resolution of capacitor, and a special arithmetic for solving the contradiction was given to make the area, speed and consumption achieve a splendid level. A novel eomparator was implemented to overcome the offset, noise, charge injection, bandwidth and speed. Fabricated in 0.35 m 2PSM CMOS technology, the ADC consumed 1.5 mW, the DNL and INL were both less than ±1 LSB.
作者 徐代果 陈光炳 刘涛
机构地区 中国电子科技集团公司第二十四研究所 模拟集成电路重点实验室
出处 《微电子学》 CAS CSCD 北大核心 2014年第5期573-577,共5页 Microelectronics
关键词 SAR ADC 电容匹配 低噪声比较器 SAR ADC Capacitor match Low noise comparator
分类号 TN432 [电子电信—微电子学与固体电子学]
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参考文献10

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同被引文献10

  • 1HARIPRASATH V, GUERBER J, LEE S H, et al. Merged capacitor switching based SAR ADC with highest switching energy-efficiency [J]. Elec Lett, 2010, 46(9):620-621.
  • 2GINSBURG B P, CHANDRAKASAN A P. An energy-efficient charge recycling approach for a SAR converter with capacitive DAC [C]// IEEE ISCAS. Kobe, Japan. 2005, 1: 184-187.
  • 3HARPE P J A, ZHOU C, BI Y, et al. A 26/xW 8 bit 10 MS/s asynchronous SAR ADC for low energy radios[J]. IEEE J Sol Sta Circ, 2011, 46(7): 1585- 1595.
  • 4NUZZO P, NANI C, ARMIENTO C, et al. A 6 bit 50 MS/s threshold configuring SAR ADC in 90-nm digital CMOS[J]. IEEE Trans Cite b- Syst I: Regu Pap, 2012, 59(1): 80-92.
  • 5RAHIMI M, GOLMAKANI A, HEYDARI M A, et al. A 10-bit low power SAR ADC with a new control logic using monotonic capacitor-switching [J]. Majlesi J Telecommun Dev, 2014, 33(1): 44-47.
  • 6LIUCC, CHANGSJ, HUANGGY, et al. A 10 b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation [C] // IEEE Int Sol Sta Circ Conf Dig Tech Pap. San Francisco, CA, USA. 2010: 386- 387.
  • 7LIUCC, CHANGSJ, HUANGGY, etal. A10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure [J]. IEEE J Sol Sta Circ, 2010, 45(4) : 731-740.
  • 8LIU C C. Design of high-speed energy-efficient successive-approximation analog-to-digital converters [D]. Tainan: National Cheng Kung University, 2010.
  • 9CHAN C H, ZHU Y, CHIO U F, et al. A reconfigurable low-noise dynamic comparator with offset calibration in 90 nm CMOS [C]// IEEE A- SSCC. Jeju, Korea. 2011: 233-236.
  • 10NUZZO P, BERNARDINIS F D, TERRENI P, et al. Noise analysis of regenerative eomparators for reconfigurabIe ADC architectures [J]. IEEE Trans Circ & Syst I: Regu Pap, 2008: 55(6): 1441-1454.

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微电子学
2014年 第5期

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