一种10位200 MHz流水线模数转换器的设计

Design of a 10-Bit 200 MHz Pipeline ADC

提出了一种10位200MHz高速流水线型模数转换器。该转换器共有9级,其中1到8级采用1.5位每级结构,最后一级采用2位闪速型模数转换器结构。设计中使用带增益自举的套筒式共源共栅运放,可同时获得高增益和大带宽,并通过运放共享技术提高工作速度。采用改进的数字校正算法,将运算分配到数字码的延迟步骤中,减少运算时间。仿真结果显示,在192MHz的采样速度下,模数转换器的有效位为8.9,SNR为58.3dB,SFDR为62.8dB,其他动态和静态特性也达到了较好的指标。

A 10-bit 200 MHz high-speed pipeline ADC was proposed. The ADC consisted of 9 stages, in which 1.5-bit/stage was applied from 1st to 8th stage and the last stage was a 2-bit flash ADC. In this design a gainboosted telescope cascode operational amplifier was used to achieve both high gain and large bandwidth, meanwhile op-amp sharing technique was used to improve the speed. Digital calibration operation was distributed into delay steps of digital codes through a modified algorithm, which could reduce time consumption. The simulation results showed that with 192 MHz sampling rate, the effective bit was 8.9, SNR was 58.3 dB, SFDR was 62.8 dB, while other dynamic and static parameters were both nice.