一种自校准全数字TDC的设计

An All-Digital Time-to-Digital Converter with Self-Calibration

随着工艺技术的进步,基于CMOS工艺的全数字时间数字转换器(TDC)受到了广泛关注,在测量、测距、计量等领域得到了广泛应用。提出了一种具有自校准算法、结构简单、测量精度稳定的全数字TDC设计方案。可通过专用全数字集成电路设计流程进行快速设计并实现,电路具有面积小、功耗低、成本低、可移植性强等优点。使用Verilog HDL语言进行RTL级描述,运用Design Compiler进行综合,产生门级网表,通过VCS和Hspice进行仿真验证。应用自校准算法后,与现有的TDC设计方法相比,电路的INL得到了明显提高,满足大量程、稳定精度的测量要求。

With the development of the CMOS process, more and more attention is paid to the design of alldigital TDC, and it is used in different fields widely. In consideration of the situation, an area saving, low power consumption, low cost and transplantable TDC is presented which can be achieved with the design flow of digital ASIC. In addition, it doesn＇t only perform self-calibration, but also features as simple architecture and stable measure precision. The RTL description is done by Verilog HDL firstly. Then, the gate-level netlist is synthesized by the DC followed with the VCS and Hspice simulation. Compared with the TDC available now, besides the INL is improved markedly, the TDC designed achieves wide dynamic range and stable measure precision after applied with the self-calibration method.