宽范围连续速率时钟数据恢复电路的设计

Design of a Wide-Range Continuous-Rate Clock and Data Recovery Circuit

采用0.18μm CMOS工艺,设计了一种连续速率时钟与数据恢复（CDR）电路。该CDR电路主要由全速率鉴频鉴相器、多频带环形压控振荡器、电荷泵等模块组成。其中,全速率鉴频鉴相器不但具有很好的鉴频鉴相功能,而且结构简单,减小了功耗和面积。多频带环形压控振荡器不但调谐范围很宽,而且引入到环路中的调谐增益较低,解决了高振荡频率和低增益之间的矛盾问题。采用自举基准和运放的电荷泵减小了各种非理想因素的影响。仿真结果表明,该CDR电路版图尺寸为265μm×786μm,功能正常,且能恢复622~3 125Mb/s之间的伪随机数据;在1.8V电源电压下,输入伪随机速率为3 125Mb/s时,功耗为100.8mW,恢复出的数据和时钟的抖动峰峰值分别为5.38ps和4.81ps。

A continuous-rate clock and data recovery circuit was designed in 0.18 /zm CMOS process. The CDR circuit included mainly a full-rate bang-bang phase frequency detector, multi-band ring voltage-controlled oscillator （VCO）, charge pump and other modules. The full-rate phase detector PFD not only had good functions, but also had simple structure, low power consumption and area. Multi-band ring voltage-controlled oscillator not only had a wide tuning range, but also had a low tuning loop gain, which had settled the conflict between high oscillating frequency and low tuning gain. By using the charge pump through bootstrap reference and op amp, various non-ideal factors were reduced. Simulation results showed that the circuit was working properly, the CDR circuit could recover the NRZ data from 622 to 3 125 Mb/s. The core size was 265 μm × 786 μm. At 1.8 V supply voltage and 3 125 Mb/s input pseudo-random rate, the power consumption was 100.8 mW, the recovered data and clock jitter peak was 5.38 ps and 4.81 ps respectively.