SAR ADC中一种比较器失调和噪声容忍的模型

Low Power Offset and Noise Tolerant Model for Comparators of SAR ADC

提出了一种针对逐次逼近型(SAR)模数转换器(ADC)中比较器失调和噪声容忍的低功耗模型。该模型在前n-m-1个比较周期引入一个快速低功耗的"差"比较器,从而减少高性能大功耗的"好"比较器的工作周期,并且通过第m+2周期的冗余电容和正常比较器的输出修正低功耗比较器的误差,从而实现单个"好"比较器工作时的性能。模型的容忍能力达到±2m LSB(最小权重位)。基于该模型,在0.13μm CMOS(互补金属氧化物半导体)工艺下设计并仿真了一个10位100 MS/s SAR ADC。版图提取参数后仿真得到SAR ADC在1.2 V电源下能够达到9.27位有效位数(ENOB),以及2.01 mW的功耗和33 fJ/conv的品质因数(FoM)。

A lower power digital correction model for comparator offset and noise tolerance of successive approximation register （SAR） analog-to-digital converter （ADC） is presented. A fine comparator with smaller offset and noise has penalty of higher power and lower speed. This model involves a faster coarse comparator with less power in the first （n-m-1） cycles to relax those penalties. The errors of the coarse comparator are tolerated by the fine comparator through the redundant comparison cycle and the capacitor at （m＋2） cycle. This model is able to tolerate noise and offset errors up to ＆#177;2mleast significant bit （LSB）. A prototype of 10 bit 100 MS/s SAR ADC with this model is simulated in a 0.13μmCMOS technology. The post-simulation results of the prototype layout witnessed an effective number of bits （ENOB） of 9.27 bit are achieved at 100 MS/s with a power consumption of 2.01 mW under 1.2 V supply, resulting in a figure of merit （FoM） of 33 fJ/conv.