期刊文献+

一种热量约束下的3D-ICs调度测试划分方法 被引量:4

A Scheduling Test Partitioning Method under Thermally Constrained for 3D Integrated Circuits
下载PDF
导出
摘要 提出了一种热量约束下的3D-ICs(三维堆叠集成电路)调度测试划分方法,该方法在充分考虑分区条件和不违反温度约束的条件下将每个测试按照原来测试的温度进行划分,允许与更多的测试并行执行,实现测试间的最大重叠。在ITC’02基准电路的实验结果表明,在温度有显著影响的环境中,与传统的方法比较该划分方法对调度质量有实质性的改进,利用测试时间的重叠可以有效地减少测试应用时间,降低测试成本。 A Scheduling Test Partitioning Method under Thermally Constrained for 3D stacked Integrated Cir- cuits was presented. The method considering the partition conditions and does not violate temperature constraints of each test are divided according to the original test temperature, allowing more tests parallel execution, to achieve the maximum overlap between tests. The experimental results on the ITC' 02 benchmark circuits show that, in envi- ronments where temperature has a significant impact, the partitioning method can improvement the scheduling quali- ty, can effectively reduce the test application time and the test cost, compared with the traditional method.
出处 《科学技术与工程》 北大核心 2014年第31期252-255,共4页 Science Technology and Engineering
基金 湖南省科技厅科技计划项目(2013FJ3077) 湖南省教育厅资助科研项目(12C1084) 衡阳市科技计划项目(2012KJ31) 湖南省"十二五"重点建设学科资助项目(湘教发[2011]76号)资助
关键词 热量约束 三维堆叠集成电路 调度测试 划分 thermally constrain three dimensional stacked integrated circuits test scheduling partitioning
  • 相关文献

参考文献10

  • 1He Z,Peng Z,Eles P.A heuristic for thermal-safe SoC test scheduling.IEEE International Test Conference,IEEE,2007 ;1-10.
  • 2Hussin F A,Yu T E C,Yoneda T,et al.RedSOCs-3D:thermal-safe test scheduling for 3D-stacked SOC.2010 IEEE Asia Pacific Conference on Circuits and Systems,IEEE,2010:264-267.
  • 3Millican S K,Saluja K K.Linear programming formulations for thermal-aware test scheduling of 3D-stacked integrated circuits.IEEE 21 st Asian Test Symposium,Niigata,Japan:IEEE,2012:37-42.
  • 4He Z,Peng Z,Eles P.Power constrained and defect-probability driven SoC test scheduling with test set partitioning.Design,Automation & Test in Europe,IEEE,2006;1-6.
  • 5Yao C,Saluja K K,Ramanathan P.Partition based SoC test scheduling with thermal and power constraints under deep submicron technologies.Asian Test Symposium,IEEE,2009 ;281-286.
  • 6王伟,林卓伟,陈田,刘军,方芳,吴玺.功耗约束下的3D多核芯片芯核级测试调度算法[J].电子测量与仪器学报,2012,26(7):591-596. 被引量:11
  • 7Millican S K,Saluja K K.A test partitioning technique for scheduling tests for thermally constrained 3D integrated circuits.27th International Conference on VLSI Design and 13th International Conference on Embedded Systems,IEEE,2014:20-25.
  • 8Yao C,Saluja K K,Ramanathan P.Power and thermal constrained test scheduling under deep submicron technologies.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2011 ;30(2):317-322.
  • 9Skadron K,Stan M,Huang W,et al.Temperature-aware microarchitecture.30th Annual International Symposium on Computer Architecture,Proceedings,IEEE Comput Soc,2003:2-13.
  • 10Millican S K,Saluja K K.3D-IC Benchmarks.2013,[Online].Available:http://3dsocbench.ece.wisc.edu/.

二级参考文献6

共引文献10

同被引文献24

  • 1朱海峰.电路板自动钻孔机的开发[J].工业控制计算机,2004,17(12):17-18. 被引量:7
  • 2AGHAEE N, PENG Z, ELES P. Process-Variation Aware Multi-temperature Test Scheduling[C]. VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on. IEEE, 2014: 32-37.
  • 3HE Z, PENG Z, ELES P. Multi-temperature testing for core-based system-on-chip-C]. Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Assoc[ation, 2010: 208-213.
  • 4MARINISSEN [J, VERBRE[J, KONIJNENBU- RG M. A structured and scalable test access architecture for TSV-based 3D stacked ICs-C3. VLSI Test Symposium (VTS), 2010 28th. IEEE, 2010 269-274.
  • 5YAO C, SALUJA K K, RAMANATHAN P. The- rma[aware test scheduling using on-chip temperature sensors['C]. VLSI Design (VLSI Design), 2011 24th International Conference on. IEEE, 20115 376-381.
  • 6AGHAEE N, PENG Z, ELES P. Adaptive tempe- rature-aware SoC test scheduling considering process variation-C]. Digital System Design (DSD), 2011 14th Euromicro Conference on. IEEE, 2011.. 197-204.
  • 7AGHAEE G N, PENG Z, ELES P. Process-vari- ation and temperature aware SoC test scheduling technique EC3. Journal of Electronic Testing, 2013, 29(4) :449-520.
  • 8王伟,林卓伟,陈田,刘军,方芳,吴玺.功耗约束下的3D多核芯片芯核级测试调度算法[J].电子测量与仪器学报,2012,26(7):591-596. 被引量:11
  • 9赖锦辉,梁松.基于层次化调度策略和动态数据复制的网格调度方法[J].计算机应用研究,2014,31(2):412-416. 被引量:3
  • 10崔小乐,熊志天,程伟,李崇仁.热感知的SoC蚁群优化测试调度方法[J].仪器仪表学报,2014,35(4):948-953. 被引量:7

引证文献4

二级引证文献10

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部