摘要
A stable LDO using VCCS （voltage control current source） is presented. The LDO is designed and implemented on GF 2P4M 0.35μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real stable LDO with a small on-chip capacitor of 1 pF, whose stability is not affected by the variable ESR （equivalent series resistance） of the output capacitor. The unit gain frequency of the LDO loop can achieve 1.5 MHz, improving the transient response. The PSR of the LDO is larger than 45 dB within 0-40 kHz. The static current of the LDO at heavy load of 100 mA is 57 μA and the dropout voltage of the LDO is 150 mV. Experimental results show that a setting time of 10 ks is achieved, and the variation of output voltage is smaller than 35 mV for a 100 mA load step in transient response of the LDO.
A stable LDO using VCCS （voltage control current source） is presented. The LDO is designed and implemented on GF 2P4M 0.35μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real stable LDO with a small on-chip capacitor of 1 pF, whose stability is not affected by the variable ESR （equivalent series resistance） of the output capacitor. The unit gain frequency of the LDO loop can achieve 1.5 MHz, improving the transient response. The PSR of the LDO is larger than 45 dB within 0-40 kHz. The static current of the LDO at heavy load of 100 mA is 57 μA and the dropout voltage of the LDO is 150 mV. Experimental results show that a setting time of 10 ks is achieved, and the variation of output voltage is smaller than 35 mV for a 100 mA load step in transient response of the LDO.
基金
supported by State Key Laboratory of ASIC and Systems of Fudan University and NSF(No.61076027)
