高速率低功耗FIR数字滤波器实现

Implementation of High-speed and Low-power Consumption FIR Digital Filters

利用硬件描述语言在ASIC上对FIR数字滤波器进行了设计和综合。利用子项空间技术有效地减少了多常系数乘法中加法器的个数,并通过限制加法器深度来进一步降低高速率约束条件下的实现难度。综合结果表明,该方法可以有效降低硬件的实现面积,适用于高吞吐率低功耗的数字系统设计。

In this paper, a hardware technique for implementing FIR filters on ASIC is proposed. The coefficient multipliers are realized with shiflers and adders. The subexpression space technology is adopted, which can effectively reduce the number of adders in the filter. In order to reduce the complexity of implementation, the adder depth is limited under the high rate constraints. The results of hardware synthesis show that the proposed meth- od can efficiently save area consumption, which can be used to design the high throughput digital systems.