JESD204B接口协议中的加扰电路设计

Implementation of Scrambler Circuit Based on JESD204B Interface Protocol

数据加扰有助于避免在高速串行传输中出现频谱杂散,对JESD204B协议规定的加扰电路进行了具体设计和实现。首先详细描述了协议要求,以8位并行加扰为例阐述了自同步加扰和解扰的电路原理,最后根据解扰器输出状态与初始状态值有关这一问题提出了改进的电路结构以及关键设计代码。仿真结果表明,该改进电路完全满足协议要求,可应用于JESD204B规范的高速串行接口电路设计。

Data scrambling contributes to avoid spurious spectral in high-speed serial transmission. A scrambler circuit is designed and implemented in this article to meet the JESD204B protocol. Firstly, a detailed description of the protocol requirements is given and the self-synchronizing scrambling and descrambling circuit principle is described by the example of eight parallel scrambling. At last, an improved circuit structure is proposed on the issue descrambler output relating to the initial state value and the key design code. Simulation results show that the circuit fully meets requirements in the protocol and can be applied in high-speed interface circuit design specified in JESD204B.