SRIO总线技术研究及其FPGA实现

Research on SRIO Bus Technology and Its Implementation Based on FPGA

针对Series Rapid IO(SRIO)总线在嵌入式系统方面的应用,根据FPGA资源丰富、设计灵活的特点,设计了一种基于Xilinx FPGA的SRIO总线接口实现方案。编写用户逻辑程序,使用FPGA IP核对SRIO总线数据进行接收、解析和发送。详细论述了硬件设计要点和软件流程,对SRIO总线协议进行了简要介绍,描述了SRIO总线的本地端点和远端端点的访问的实现过程。通过试验测试了SRIO总线速度,验证了SRIO接口工作的正确性。

Aiming at the application of embedded system of SRIO,a scheme is proposed to realize SRIO bus interface based on Xilinx FPGA on the basis of such characteristics as abundant resources and flexible designing of FPGA. The user logic program is compiled,and the SRIO bus data are received,decoded and sent by using FPGA IP core. The hardware design and software flow are discussed in detail. This paper describes the protocol of SRIO bus,the implementation of local endpoint and remote endpoint accessing. The speed of SRIO bus is tested and the correctness of SRIO interface operation is validated through experiments.