一种具有延迟校准功能的可编程多相位时钟电路

Programmable mlti-phase clock circuit with delay calibration

基于延迟锁相环原理,提出了一种新型的具有延迟校准功能的可编程多相位时钟电路,能为工作在80MHz的电荷耦合器件信号处理器提供精度高达390ps的时序信号.将主时钟的单周期等分为32份,通过可编程相位组合电路,产生相位及占空比可调的信号,能满足不同电荷耦合器件所需的最优工作时序.传统的延迟锁相环结构随着延迟单元的增加,延迟单元之间不匹配愈加明显,导致输出相位偏离理想位置.引入延迟校准电路可以显著降低相位之间的误差,校准后的多相位时钟信号接入可编程相位组合器进行选择组合,产生所需的高精度时序信号.基于SMIC 0.18μm 3.3VCMOS工艺完成设计,在80MHz主时钟下的后仿真结果表明：电路可产生占空比范围为2%-98%的输出时钟,校准后的延迟误差小于5ps,边到边抖动为1.14ps,有效地保证了相位精度.

Based on the principle of the delay-locked loop （DLL）,this paper introduces a programmable multi-phase clock circuit with a delay calibration loop.The proposed circuit offers a clock signal with a precision of 390 ps and optimum timing for a variety of CCD signal processors.One cycle of the main clock is divided into 32 parts equally,while timing with a tunable duty cycle is generated by the programmable phase combiner.The increase in delay elements worsens the delay time error between different phases of the output signals,and hence a delay time calibration loop is applied to suppress this effect.In SMIC 0.1 8μm 3.3 V CMOS process,with a 80 MHz main clock,the post simulation results show that the proposed circuit generates an output clock with a 2%~98% duty cycle,a 1.14 ps edge to edge jitter and a less than 5 ps calibrated delay time error.